1. Field of the Invention
This invention generally relates to methods and systems for extracting comprehensive design guidance for in-line process control of wafers.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers. Inspection processes have always been an important part of fabricating semiconductor devices such as integrated circuits. However, as the dimensions of semiconductor devices decrease, inspection processes become even more important to the successful manufacture of acceptable semiconductor devices. For instance, as the dimensions of semiconductor devices decrease, detection of defects of decreasing size has become necessary since even relatively small defects may cause unwanted aberrations in the semiconductor devices.
Other process control may be performed on a wafer during or after fabrication of a device on the wafer. For example, once a wafer has been inspected for defects, one or more defects detected in the inspection may be reviewed in a defect review process. The defect review process may be performed on a different tool than that used for inspection, which may be optimized for defect review. Additional information generated during the defect review process may be used to classify and/or filter the defects detected on the wafer. Metrology processes may also be performed on wafers. In these processes, one or more characteristics of the wafer such as linewidth, film thickness and the like are measured. These processes may also be performed by tools that are optimized for and dedicated to metrology. In addition, failure analysis (FA) processes may be performed on wafers in which information about physical characteristics of the wafers is determined, usually based on electrical testing results for the wafers.
In some instances, process control for wafer fabrication such as the examples described above is performed based on the design of the device being formed on the wafer. For example, some guidance for in-line inspection, review, and metrology is beginning to come from design teams today. However, such guidance usually covers only a relatively small segment of what the design teams know about their chip designs and what could be substantially useful for in-line inspection and metrology. In addition, there is a substantially marked lack of automation used to create such guidance today.
There are, therefore, a number of disadvantages to the current methods and systems for guiding process control based on design data. For example, the currently used methods are slow to the point of being impractical to cover the entire spectrum of a design team's knowledge about their chip design. In addition, some types of design teams' knowledge are easier than others for in-line inspection and metrology systems to consume, e.g., design-for-manufacturing (DFM) errors, physical FA locations picked by product engineering analysis, etc. Furthermore, the scale of such inputs remains a substantially small percentage of actual observations due to lack of automation.
Accordingly, it would be advantageous to develop methods and systems for extracting comprehensive design guidance for in-line process control of wafers that do not have one or more of the disadvantages described above.